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NXP Semiconductors /LPC43xx /SDMMC /PLDMND

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Interpret as PLDMND

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PD

Description

Poll Demand Register

Fields

PD

Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data